library ieee;
use ieee.std_logic_1164.all;

entity shiftRegSelectLogic is
	port (
		clk, clr, load, hold : in bit;
		z1, z2 : out bit
	);
end entity shiftRegSelectLogic;

architecture DATAFLOW of shiftRegSelectLogic is
    
    signal orOut : bit_vector(1 downto 0);
    signal andOut : bit_vector(1 downto 0);
    
    begin
		orOut(0) <= hold or clr;
		orOut(1) <= load or clr;
		andOut(0) <= orOut(0) and (not load);
		andOut(1) <= orOut(1) and (not hold);
		
		z1 <= andOut(0);
		z2 <= andOut(1);
    
end architecture DATAFLOW;

architecture STRUCTURAL of shiftRegSelectLogic is
	
	component and2
	
	port(a,b : in bit;
		z : out bit
	);
	
	end component;
	
	component notDataFlow
	
	port(a : in bit;
		z : out bit
		);
	end component;
	
	component or2
	
	port(a,b : in bit;
		z : out bit
	);
	
	end component;
	
	for all : and2 use entity work.and2(DATAFLOW); 
	for all : notDataFlow use entity work.notDataFlow(DATAFLOW);
	for all : or2 use entity work.or2(DATAFLOW);
	
	signal or1Z : bit;
	signal or2Z : bit;
	signal holdNot : bit;
	signal loadNot : bit;
	
begin

	or0 : or2 port map(hold, clr, or1Z);
	or1 : or2 port map(load, clr, or2Z);
	not0 : notDataFlow port map(hold, holdNot);
	not1 : notDataFlow port map(load, loadNot);
	and0 : and2 port map(or1Z, loadNot, Z1);
	and1 : and2 port map(or2Z, holdNot, Z2);

end architecture STRUCTURAL;

architecture RTL of shiftRegSelectLogic is
    
    begin
        
        process (clr, load, hold)
        begin
                
       if (load = '1') then
           z1 <= '1';
       	   z2 <= '0'; 
   	   end if;
   	   if (hold = '1') then
           z1 <= '0';
       	   z2 <= '1';
       else 
         	z1 <= '0'; z2 <= '0';
       end if;   
   	   if (clr = '0') then
            z1 <= '1';
            z2 <= '1';
       end if;
   
    end process;
end architecture RTL;